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ISL65426
Data Sheet February 21, 2007 FN6340.2
6A Dual Synchronous Buck Regulator with Integrated MOSFETs
The ISL65426 is a high efficiency dual output monolithic synchronous buck converter operating over an input voltage range of 2.375V to 5.5V. This single chip power solution provides two output voltages which are selectable or externally adjustable from 1V to 80% of the supply voltage while delivering up to 6A of total output current. The two PWMs are synchronized 180 out of phase reducing the RMS input current and ripple voltage. The ISL65426 switches at a fixed frequency of 1MHz and utilizes current-mode control with integrated compensation to minimize the size and number of external components and provide excellent transient response. The internal synchronous power switches are optimized for good thermal performance, high efficiency, and eliminate the need for an external Schottky diode. A unique power block architecture allows partitioning of six 1A capable blocks to support one of four configuration options. One master power block is associated with each synchronous converter channel. Four floating slave power blocks allow the user to assign them to either channel. Proper external configuration of the power blocks is verified internally prior to soft-start initialization. Independent enable inputs allow for synchronization or sequencing soft-start intervals of the two converter channels. A third enable input allows additional sequencing for multi-input bias supply designs. Individual power good indicators (PG1, PG2) signal when output voltage is within regulation window. The ISL65426 integrates protection for both synchronous buck regulator channels. The fault conditions include overcurrent, undervoltage, and IC thermal monitor. High integration contained in a thin Quad Flat No-lead (QFN) package makes the ISL65426 an ideal choice to power many of today's small form factor applications. A single chip solution for large scale digital ICs, like field programmable gate arrays (FPGA), requiring separate core and I/O voltages.
Features
* High Efficiency: Up to 95% * Fixed Frequency: 1MHz * Operates From 2.375V to 5.5V Supply * 1% Reference * Flexible Output Voltage Options - Programmable 2-Bit VID Input - Adjustable Output From 0.6V to 4.0V * User-Partitioned Power Blocks * Ultra-Compact DC/DC Converter Design * PWMs Synchronized 180 Out of Phase * Independent Enable Inputs and System Enable * Stable All Ceramic Solutions * Excellent Dynamic Response * Independent Output Digital Soft-Start * Power Good Output Voltage Monitor * Short-Circuit and Thermal-Overload Protection * Overcurrent and Undervoltage Protection * Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
* FPGA, CPLD, DSP, and CPU Core and I/O Voltages - Xilinx Spartan IIITM, Virtex IITM, Virtex II ProTM, Virtex 4TM - Altera StratixTM, Stratix IITM, CycloneTM, Cyclone IITM - Actel FusionTM, LatticeSCTM, LatticeECTM * Low-Voltage, High-Density Distributed Power Systems * Point-of-Load Regulation * Distributed Power Systems * Set-Top Boxes
Ordering Information
PART NUMBER (Note) PART MARKING TEMP. RANGE (C) PACKAGE (Pb-free) PKG. DWG. # L50.5x10 L50.5x10
ISL65426HRZ* ISL65426 HRZ -10 to +100 50 Ld 5x10 QFN ISL65426IRZA* ISL65426 IRZ -40 to +85 50 Ld 5x10 QFN *Add "-T" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2006-2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL65426 Pinout
ISL65426 (50 LD QFN) TOP VIEW
ISET2 PG1 PG2 PGND EN1 EN2 FB1 FB2 42 PGND 41 PGND 40 PGND 39 PGND 38 LX6 37 LX6 PGND PVIN2 8 LX2 9 PGND 10 PGND 11 LX3 12 PVIN3 13 VCC 14 VCC 15 VCC 16 PGND 17 18 19 20 21 22 23 24 25 PGND ISET1 V1SET1 V1SET2 V2SET1 V2SET2 PGND 36 PVIN6 35 PVIN5 34 LX5 33 PGND 32 PGND 31 LX4 30 PVIN4 29 PGND 28 PGND 27 GND 26 GND
50 49 48 47 46 45 44 43 PGND 1 PGND 2 PGND 3 PGND 4 LX1 5 LX1 6 PVIN1 7
EN
2
FN6340.2 February 21, 2007
ISL65426 Typical Application Schematics
SINGLE INPUT SUPPLY
3.3V
PG1 EN1 EN2 3.3V PVIN1 3.3V 22F C1 PVIN2 EN
PG2
PVIN6 3.3V PVIN5 C4 22F
PVIN3
PVIN4
LX1 L1 1.2V 3A C2 200F 1H LX2
LX6 L2 LX5 1H C3 200F 2.5V 3A
ISL65426
LX3 FB1 LX4 FB2
VCC
3.3V C5 0.1F
GND
PGND V1SET1 V2SET2 V1SET2 V2SET1 ISET1 ISET2
3.3V
FIGURE 1. TYPICAL APPLICATION FOR 3A:3A CONFIGURATION
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FN6340.2 February 21, 2007
ISL65426 Typical Application Schematics (Continued)
DUAL INPUT SUPPLY
3.3V
PG1 EN1 EN2 5.0V PVIN1 PVIN2 5.0V 22F C1 PVIN3 PVIN4 EN
PG2
PVIN6 3.3V PVIN5 C4 22F
LX6 LX5 L2 1.0H 1.8V 2A
ISL65426
LX1 L1 1.5V 4A 0.6H C2 200F LX2 LX3 LX4 VCC FB2
C3 100F
5.0V C5 0.1F
FB1 GND
PGND V2SET1 V1SET2 V1SET1 V2SET2 ISET1 ISET2
3.3V
FIGURE 2. TYPICAL APPLICATION FOR 4A:2A CONFIGURATION
4
FN6340.2 February 21, 2007
ISL65426 Typical Application Schematics (Continued)
5.0V
PG1 EN1 EN2 5.0V PVIN1 PVIN2 5.0V C2 22F C1 22F PVIN3 PVIN4 PVIN6 EN
PG2
PVIN5 C4 22F
5.0V
LX5 LX1 LX2 L1 1.0H C2 330F 2.5V 5A 31.6k 10k LX3 LX4 LX6 VCC FB2
L2 2.2H C3 100F 3.3V 1A
ISL65426
5.0V C5 0.1F
FB1 GND
PGND V2SET2 V2SET1 V1SET1 V1SET2 ISET2 ISET1
5.0V
FIGURE 3. TYPICAL APPLICATION FOR 5A:1A CONFIGURATION
5
FN6340.2 February 21, 2007
ISL65426 Functional Block Diagram
EN2 EN VCC GND EN1
POWER-ON RESET (POR)
PVINx
PVINx
CURRENT SENSE SOFT START SLOPE COMPENSATION PWM CONTROL LOGIC
FB1
EA
GM
GATE DRIVE
LXx
V1SET1 V1SET2
OUTPUT VOLTAGE CONFIG
COMPENSATION EPAD GND
PGOOD1
UV POWER GOOD SOFT START POWER DEVICE CONFIG ISET1 ISET2
PWM REFERENCE 0.60V
THERMAL MONITOR
PVINx POR SOFT START SLOPE COMPENSATION PWM CONTROL LOGIC
CURRENT SENSE
FB2 V2SET1 V2SET2
EA
GM
GATE DRIVE
LXx
OUTPUT VOLTAGE CONFIG
COMPENSATION EPAD GND
OV UV POWER GOOD
PGOOD2
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FN6340.2 February 21, 2007
ISL65426
Absolute Maximum Ratings
VCC, PVINx, LXx . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.3V to +6V FBx, ENx, VxSETx, ISETx, PGOODx . . . . . . . . -0.3V to VCC+0.3V ESD Classification Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200V
Thermal Information
Thermal Resistance JA (C/W) JC (C/W) QFN Package (Notes 1, 2). . . . . . . . . . 23 2.5 Maximum Junction Temperature (Plastic Package) . . . . . . . +150C Maximum Storage Temperature Range . . . . . . . . . .-65C to +150C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +260C Ambient Temperature Range (ISL65426HRZ). . . . .-10C to +100C Ambient Temperature Range (ISL65426IRZA) . . . . .-40C to +85C Operating Junction Temperature Range . . . . . . . . .-10C to +125C
Recommended Operating Input Range
VCC, PVINx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.375V to +5.5V
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. 150C max junction temperature is intended for short periods of time to prevent shortening the lifetime. Operation close to 150C junction may trigger the shutdown of the device even before 150C, since this number is specified as typical.
NOTES: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379 for details. 2. For JC, the "case temp" location is the center of the exposed metal pad on the package underside. See Tech Brief TB379 for details.
Electrical Specifications
PARAMETER POWER SUPPLY Quiescent Supply Current Shutdown Supply Current
Recommended operating conditions unless otherwise noted. VCC = PVIN = 5.0V, TA = -10C to +100C for ISL65426HRZ and TA = -40C to +85C for ISL65426IRZA. (Note 2) TEST CONDITIONS MIN TYP MAX UNITS
EN1 = EN2 = EN = VCC = 5V, IOUT1 = IOUT2 = 0mA EN1 = EN2 = EN = GND, VCC = PVIN = 5.5V EN1 = EN2 = EN = GND, VCC = PVIN = 3.3V EN1 = EN2 = EN = GND, VCC = PVIN = 2.375V
30 5.4 2.8 1.7 7 3.2
mA mA mA mA
PHASE CONFIGURATION LX Pull Down LX Output Leakage LX1,LX3, LX4, LX5, LX6 Only - Configuration Only Low Level, Single LX output High Level, Single LX output Minimum Controllable ON time OUTPUT VOLTAGE TOLERANCE Reference Voltage Tolerance TJ = -40C to +100C TJ = 100C to +125C Programmed Output Voltage Tolerance OSCILLATOR Accuracy Maximum LX Pulse Width Minimum LX Pulse Width OUTPUT VOLTAGE SELECTION VxSETx Input High Threshold VxSETx Pull Down POWER BLOCKS ISETx Input High Threshold ISETx Pull Up 0.4 7 1.2 10 1.5 15 V A 0.4 7 1.2 10 1.5 15 V A 0.85 1 950 50 1.15 MHz ns ns TJ = -40C to +125C 0.594 0.591 2 0.6 0.6 0.606 0.609 2 V V % (Note 3) -5 -5 125 1 5 5 mA A A ns
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FN6340.2 February 21, 2007
ISL65426
Electrical Specifications
PARAMETER Maximum Output Current Recommended operating conditions unless otherwise noted. VCC = PVIN = 5.0V, TA = -10C to +100C for ISL65426HRZ and TA = -40C to +85C for ISL65426IRZA. (Note 2) (Continued) TEST CONDITIONS Per Block; VCC = PVIN = 5.0V; VOUT = 1.8V (Note 3) Per Block; VCC = PVIN = 2.375V; VOUT = 1.2V (Note 3) Peak Output Current Limit Upper Device rDS(ON) Lower Device rDS(ON) Efficiency Per Block 0.4A Per Block, VCC = PVIN = 3.3V, VOUT = 1.8V 0.4A Per Block, VCC = PVIN = 3.3V, VOUT = 1.8V 0.5A Per Block, VCC = PVIN = 3.3V, VOUT = 1.1V 0.5A Per Block, VCC = PVIN = 5V, VOUT = 2.5V POWER-ON RESET AND ENABLE PINS VCC POR Threshold VCC Rising VCC Falling PVIN POR Threshold PVIN Rising; Configuration 5:1 PVIN Falling; Configuration 5:1 PVIN Bias Output Voltage Enable Threshold VOUT2 = 3.3V; VCC = PVIN VOUT2 = 2.5V; VCC = PVIN EN1/EN2 Threshold Rising Threshold; VCC = 5V Hysteresis Rising Threshold; VCC = 3.3V Hysteresis Rising Threshold; VCC = 2.375V Hysteresis EN1/EN2 Pull Up EN Threshold EN Sink Current Soft-Start Time POWER GOOD SIGNAL Rising Threshold Rising Hysteresis Falling Threshold Falling Hysteresis Power Good Drive Power Good Leakage PROTECTION FEATURES Undervoltage Monitor Undervoltage Trip Threshold Undervoltage Recovery Threshold THERMAL MONITOR Thermal Shutdown Temperature (Note 3) NOTE: 3. Not production tested. 150 C As % of VREF As % of VREF 70 82 75 89 80 95 % % As % of VREF; VOUT1 = 1.8V; VOUT2 = 3.3V As % of VREF; VOUT1 = 1.8V; VOUT2 = 3.3V As % of VREF; VOUT1 = 1.8V; VOUT2 = 3.3V As % of VREF; VOUT1 = 1.8V; VOUT2 = 3.3V VCC = 5V; PG1 = PG2 = 0.4V 110 5 80 4 1 1 115 7 85 7 120 9 90 9 % % % % mA A EN = GND 7 0.57 7 0.55 0.75 2.15 2.05 1.9 1.75 4.1 2.8 1.0 2.25 2.15 2.05 1.90 4.3 2.9 1.2 280 0.98 200 0.82 185 10 0.6 11 4 15 0.63 15 1.05 1.20 2.35 2.25 2.15 2.00 4.5 3.0 1.45 V V V V V V V mV V mV V mV A V A ms 60 30 MIN 1.0 1.0 2.0 100 55 90 95 140 85 TYP MAX UNITS A A A m m % %
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FN6340.2 February 21, 2007
ISL65426 Typical Performance Curves
100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 0.1 1.0 2.0 OUTPUT LOAD (A) 3.0 4.0 3.3VIN 5.5VIN 2.5VIN EFFICIENCY (%)
Circuit of Figure 2. VIN = 5V, IOUT1 = 4A, IOUT2 = 2A, TA = -10C to +100C unless otherwise noted. Typical values are at TA = +25C.
100 90 80 70 60 50 40 30 20 10 0 0.1 1.0 2.0 OUTPUT LOAD (A) 3.0 4.0 3.3VIN 5.5VIN 2.5VIN
FIGURE 4. VOUT1 = 1.2V EFFICIENCY vs LOAD
FIGURE 5. VOUT1 = 1.5V EFFICIENCY vs LOAD
100 90 80 EFFICIENCY (%) EFFICIENCY (%) 70 60 50 40 30 20 10 0 0.1 1.0 2.0 OUTPUT LOAD (A) 3.0 4.0 3.3VIN 5.5VIN 2.5VIN
100 90 80 70 60 50 40 30 20 10 0 0.1 0.5 1.0 OUTPUT LOAD (A) 1.5 2.0 3.3VIN 5.5VIN 2.5VIN
FIGURE 6. VOUT1 = 1.8V EFFICIENCY vs LOAD
FIGURE 7. VOUT2 = 1.8V EFFICIENCY vs LOAD
100 90 80 EFFICIENCY (%) 4VIN
100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 0.1 0.5 1.0 OUTPUT LOAD (A) 1.5 2.0 0.1 0.5 1.0 OUTPUT LOAD (A) 1.5 2.0 5VIN 4.5VIN 5.5VIN
70 60 50 40 30 20 10 0 3VIN 5.5VIN
FIGURE 8. VOUT2 = 2.5V EFFICIENCY VS LOAD
FIGURE 9. VOUT2 = 3.3V EFFICIENCY vs LOAD
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FN6340.2 February 21, 2007
ISL65426 Typical Performance Curves
1.235 1.225 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 1.215 5.5VIN 1.205 1.195 1.185 1.175 1.165 0.1 2.5VIN 3.3VIN
Circuit of Figure 2. VIN = 5V, IOUT1 = 4A, IOUT2 = 2A, TA = -10C to +100C unless otherwise noted. Typical values are at TA = +25C. (Continued)
1.235 1.225 1.215 NO LOAD 1.205 1.195 1.185 1.175 1.165 2.0 4A LOAD 2A LOAD
1.0
2.0 OUTPUT LOAD (A)
3.0
4.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
INPUT VOLTAGE (V)
FIGURE 10. VOUT1 = 1.2V REGULATION vs LOAD
FIGURE 11. VOUT1 = 1.2V REGULATION vs VIN
1.545 1.535 OUTPUT VOLTAGE (V) 5.5VIN OUTPUT VOLTAGE (V) 1.525 1.515 1.505 1.495 1.485 1.475 1.465 1.455 0.1 1.0 2.0 OUTPUT LOAD (A) 2.5VIN 3.3VIN 3.0 4.0
1.545 1.535 1.525 1.515 1.505 1.495 1.485 1.475 1.465 1.455 2.0 2.5 3.0 3.5 4A LOAD NO LOAD 2A LOAD
4.0
4.5
5.0
5.5
INPUT VOLTAGE (V)
FIGURE 12. VOUT1 = 1.5V REGULATION vs LOAD
FIGURE 13. VOUT1 = 1.5V REGULATION vs VIN
1.845
1.845
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
1.825 5.5VIN 1.805
1.825 2A LOAD NO LOAD 1.805
1.785
1.785
1.765
2.5VIN
3.3VIN
1.765
4A LOAD
1.745 0.1
1.0
2.0 OUTPUT LOAD (A)
3.0
4.0
1.745 2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
INPUT VOLTAGE (V)
FIGURE 14. VOUT1 = 1.8V REGULATION vs LOAD
FIGURE 15. VOUT1 = 1.8V REGULATION vs VIN
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FN6340.2 February 21, 2007
ISL65426 Typical Performance Curves
1.845 OUTPUT VOLTAGE (V)
Circuit of Figure 2. VIN = 5V, IOUT1 = 4A, IOUT2 = 2A, TA = -10C to +100C unless otherwise noted. Typical values are at TA = +25C. (Continued)
1.845
OUTPUT VOLTAGE (V)
1.825 2.5VIN
3.3VIN
1.825 NO LOAD 1.805
1.805
1.785 5.5VIN
1.785
1.765
1.765 2A LOAD 1A LOAD 5.0 5.5
1.745 0.1
1.745 0.5 1.0 OUTPUT LOAD (A) 1.5 2.0 2.0 2.5 3.0 3.5 4.0 4.5 INPUT VOLTAGE (V)
FIGURE 16. VOUT2 = 1.8V REGULATION vs LOAD
FIGURE 17. VOUT2 = 1.8V REGULATION vs VIN
2.565 2.545 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 2.525 4VIN 2.505 2.485 2.465 2.445 2.425 0.1 5.5VIN 3.3VIN
2.565 2.545 2.525 2.505 2.485 2.465 2.445 2.425 0.5 1.0 OUTPUT LOAD (A) 1.5 2.0 2A LOAD 2.0 2.5 3.0 3.5 4.0 4.5 1A LOAD NO LOAD
5.0
5.5
INPUT VOLTAGE (V)
FIGURE 18. VOUT2 = 2.5V REGULATION vs LOAD
FIGURE 19. VOUT2 = 2.5V REGULATION vs VIN
3.400 3.380 OUTPUT VOLTAGE (V) 3.360 OUTPUT VOLTAGE (V) 3.340 3.320 3.300 3.280 3.260 3.240 3.220 3.200 0.1 0.5 1.0 OUTPUT LOAD (A) 1.5 5VIN 2.0 5.5VIN 4.5VIN
3.400 3.380 3.360 3.340 3.320 3.300 3.280 3.260 3.240 3.220 3.200 4.0 4.25 4.5 4.75 5.0 5.25 5.5 2A LOAD 1A LOAD NO LOAD
INPUT VOLTAGE (V)
FIGURE 20. VOUT2 = 3.3V REGULATION vs LOAD
FIGURE 21. VOUT2 = 3.3V REGULATION vs VIN
11
FN6340.2 February 21, 2007
ISL65426 Typical Performance Curves
Circuit of Figure 2. VIN = 5V, IOUT1 = 4A, IOUT2 = 2A, TA = -10C to +100C unless otherwise noted. Typical values are at TA = +25C. (Continued)
EN1 5V/DIV
EN1 5V/DIV
VOUT1 500mV/DIV
VOUT1 500mV/DIV
IL1 1A/DIV IL1 1A/DIV
PG1 5V/DIV
PG1 5V/DIV
FIGURE 22. START-UP VOUT1 = 1.2V (NO LOAD)
FIGURE 23. START-UP VOUT1 = 1.2V (UNDER PRE-BIASED)
EN1 5V/DIV EN1 5V/DIV VOUT1 500mV/DIV
IL1 2A/DIV
VOUT1 500mV/DIV
IL1 1A/DIV
PG1 5V/DIV
POK1 5V/DIV
FIGURE 24. START-UP VOUT1 = 1.2V (FULL LOAD)
FIGURE 25. SHUTDOWN VOUT1 = 1.2V
EN2 5V/DIV
EN2 5V/DIV
VOUT2 1V/DIV
VOUT2 1V/DIV
IL2 1A/DIV
IL2 1A/DIV
PG2 5V/DIV
PG2 5V/DIV
FIGURE 26. START-UP VOUT2 = 3.3V (NO LOAD)
FIGURE 27. START-UP VOUT2 = 3.3V (UNDER PRE-BIASED)
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FN6340.2 February 21, 2007
ISL65426 Typical Performance Curves
Circuit of Figure 2. VIN = 5V, IOUT1 = 4A, IOUT2 = 2A, TA = -10C to +100C unless otherwise noted. Typical values are at TA = +25C. (Continued)
EN2 5V/DIV VOUT1 RIPPLE 20mV/DIV VOUT2 1V/DIV IOUT1 1A/DIV IL2 1A/DIV
VOUT2 RIPPLE 20mV/DIV PG2 5V/DIV
FIGURE 28. START-UP VOUT2 = 3.3V (FULL-LOAD)
FIGURE 29. VOUT1 = 1.2V LOAD TRANSIENT
VOUT1 RIPPLE 20mV/DIV
LX1 5V/DIV
IOUT1 500mA/DIV VOUT1 500mV/DIV
VOUT2 RIPPLE 50mV/DIV IL1 5A/DIV
PG1 5V/DIV
FIGURE 30. VOUT1 = 1.2V LOAD TRANSIENT
FIGURE 31. VOUT1 = 1.2V OUTPUT SHORT CIRCUIT
LX1 5V/DIV LX2 5V/DIV
VOUT1 500mV/DIV VOUT2 1V/DIV IL2 5A/DIV IL1 5A/DIV
PG1 5V/DIV
PG2 5V/DIV
FIGURE 32. VOUT1 = 1.2V OUTPUT SHORT CIRCUIT RECOVERY
FIGURE 33. VOUT2 = 3.3V OUTPUT SHORT CIRCUIT
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FN6340.2 February 21, 2007
ISL65426 Typical Performance Curves
Circuit of Figure 2. VIN = 5V, IOUT1 = 4A, IOUT2 = 2A, TA = -10C to +100C unless otherwise noted. Typical values are at TA = +25C. (Continued)
LX2 5V/DIV
VOUT2 1V/DIV
IL2 5A/DIV
PG2 5V/DIV
FIGURE 34. VOUT2 = 3.3V OUTPUT SHORT CIRCUIT RECOVERY
ISET2
PG1
PG2
EN1
EN2
Pin Descriptions
FB2
FB1
EN
VCC
42 PGND 41 PGND 40 PGND 39 PGND 38 LX6 37 LX6
50 49 48 47 46 45 44 43 PGND 1 PGND 2 PGND 3 PGND 4 LX1 5 LX1 6 PVIN1 7 PVIN2 8 LX2 9 PGND 10 PGND 11 LX3 12 PVIN3 13 VCC 14 VCC 15 VCC 16 PGND 17 18 19 20 21 22 23 24 25 V1SET1 V1SET2 V2SET1 V2SET2 ISET1 PGND PGND PGND
The bias supply input for the small signal circuitry. Connect this pin to the highest supply voltage available if two or more options are available. Locally filter this pin using a quality 0.1F ceramic capacitor and 5 resistor (optional). PVIN1, PVIN2, PVIN3, PVIN4, PVIN5, PVIN6 These pins are the power supply pins for the corresponding PWM power blocks. Associated power blocks must all tie to the same power supply. The power supply must fall in the range of 2.375V to 5.5V. GND Signal ground. All small signal components connect to this ground, which in turn connects to PGND at one point. PGND Power ground for the PWM power blocks and thermal relief for the package. The exposed pad must be connected to PGND and soldered to the PCB. Connect these pins closely to the negative terminal of input and output capacitors. FB1, FB2 Voltage feedback input. Depending on voltage selection pin settings, connect an optional resistor divider between VOUT and GND for selection of a variable output voltage. LX1, LX2, LX3, LX4, LX5, LX6 Switch node connection to inductor. This pin connects to the internal synchronous power MOSFET switches. The average voltage of this node is equal to the regulator output voltage.
PGND
36 PVIN6 35 PVIN5 34 LX5 33 PGND 32 PGND 31 LX4 30 PVIN4 29 PGND 28 PGND 27 GND 26 GND
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FN6340.2 February 21, 2007
ISL65426
EN System enable for voltage monitoring with programmable hysteresis. This pin has a POR rising threshold of 0.6V. This enable is intended for applications where two or more input power supplies are used and bias rise time is an issue. EN1, EN2 These pins are threshold-sensitive enable inputs for the individual PWM converters. These pins have low current (10A) internal pull-ups to VCC. This pin disables the respective converter until pulled above a 1V rising threshold. ISET1, ISET2 Power block configuration inputs. Select the proper state for each pin according to Table 1. V1SET1, V1SET2, V2SET1, V2SET2 Output voltage configuration inputs. Select the proper state of each pin per the electrical specification table. PG1, PG2 Power good output. Open drain logic output that is pulled to ground when the output voltage is outside regulation limits. Each power block has a separate power supply connection pin, PVINx, and common channels must join these inputs to one input power supply. Common synchronous power switch connection points for each channel must be tied together and to an external inductor. See the "Typical Application Schematics" for pin connection guidance.
TABLE 1. POWER BLOCK CONFIGURATION I1SET I2SET IOUT1 1 1 0 0 1 0 1 0 3A 4A 5A 2A CHANNEL 1 CONNECTIONS LX1,LX2,LX3 LX1,LX2,LX3,LX4 LX1,LX2,LX3,LX4 ,LX6 LX1,LX2 IOUT2 3A 2A 1A 4A CHANNEL 2 CONNECTIONS LX4,LX5,LX6 LX5,LX6 LX5 LX3,LX4,LX5,LX6
The remaining four floating power blocks can be partitioned in one of four valid states outlined in Table 1. The controller detects the programmed configuration based on the state of logic signals at pins ISET1 and ISET2. The controller checks the power block configuration versus the programmed configuration before the either converter can soft-start.
Functional Description
The ISL65426 is a monolithic, constant frequency, currentmode dual output buck converter controller with user configurable power blocks. Designed to provide a total DC/DC solution for FPGAs, CPLDs, core processors, and ASICs.
X X
Invalid LX Configurations: SS Prevented 1A LX2 5A LX1,LX3,LX4, LX5,LX6
Each power block has a scaled pilot device providing current feedback. The configuration pin settling determines how the controller handles separation and summing of the individual current feedback signals.
PVIN1
PVIN6
POWER BLOCK 1
LX1 PVIN2
POWER BLOCK 6
LX6
Main Control Loop
The ISL65426 is a monolithic, constant frequency, currentmode step-down DC/DC converter. During normal operation, the internal top power switch is turned on at the beginning of each clock cycle. Current in the output inductor ramps up until the current comparator trips and turns off the top power MOSFET. The bottom power MOSFET turns on and the inductor current ramps down for the rest of the cycle. The current comparator compares the output current at the ripple current peak to a current pilot. The error amplifier monitors VOUT and compares it with the internal voltage reference. The error amplifier's output voltage drives a proportional current to the pilot. If VOUT is low the pilot's current level is increased and the trip off current level of the output is increased. The increased current works to raise the VOUT level into agreement with the voltage reference.
PVIN5
POWER BLOCK 2
LX2
POWER BLOCK 5
LX5
PVIN3
PVIN4
POWER BLOCK 3
LX3
POWER BLOCK 4
LX4
MASTER POWER BLOCK FLOATING POWER BLOCK
FIGURE 35. POWER BLOCK DIAGRAM
Power Blocks
A unique power block architecture allows partitioning of six 1A capable modules to support one of four power block configuration options. The block diagram in Figure 3 provides a top level view of the power block layout. One master power block is assigned to each converter output channel. Power Block 2 is allotted to converter Channel 1 and Power Block 5 to Channel 2. The master power blocks must not be tied together or the controller will not soft-start. 15
Output Voltage Programming
The feedback voltage applied to the inverting input of the error amplifier is scaled internally relative to the 0.6V internal reference voltage based on the state of logic signals at pins V1SET1, V1SET2, V2SET1 and V2SET2. The output voltage configuration logic decodes the 2-bit voltage identification codes into one of the discrete voltages shown
FN6340.2 February 21, 2007
ISL65426
in Table 2. When Each pin is pulled to GND by an internal 10A pull down, this default condition programs the output voltage to the lowest level. The pull down prevents situations where a pin could be left floating for example (cold solder joint) from causing the output voltage to rise above the programmed level and damage a sensitive load device.
TABLE 2. OUTPUT VOLTAGE PROGRAMMING VOUT1 1.8V 1.5V 1.2V 0.6V V1SET1 1 0 1 0 V1SET2 1 1 0 0 VOUT2 3.3V 2.5V 1.8V 0.6V V2SET1 1 0 1 0 V2SET2 1 1 0 0
commanded output voltage is within the proper window of operation, the power good signal corresponding to the active channel changes state from low to high indicating proper operation initialization.
Power-On Reset
The POR circuitry prevents the controller from attempting to soft-start before sufficient bias is present at vital power supply input pins. These include the VCC and PVINx pins. The VCC pins have a variable POR threshold based on the output voltage configuration pin configuration of VOUT2. If the configuration pins are set for 2.5V, the VCC POR rising threshold is typically 2.9V. The 3.3V configuration increases the VCC POR level to 4.3V. This variable rising threshold guarantees that the controller can properly switch the internal power blocks at the assigned output voltage levels. The PVINx pins have a set POR rising threshold for all output voltage configurations. While the voltage on these pins are below this threshold, as defined in the "Electrical Specifications" table on page 7, the controller inhibits switching of the internal power MOSFETs. Built-in hysteresis between the rising and falling thresholds insures that once enabled, the controller will not inadvertently toggle turn off unless the bias voltage drops substantially. While these pins are below the POR rising threshold, the synchronous power switch LX pins are held in a high-impedance state. If additional POR control is required, a system enable input can be used to govern initialization as described in the next section.
ISL65426
EXTERNAL CONDITIONS
LOUT LX COUT
VOUT 1.4V
R1 13.3k FB R2 10k
FIGURE 36. EXTERNAL OUTPUT VOLTAGE SELECTION
For designers requiring an output voltage level outside those shown Table 2, the ISL65426 allows user programming with an external resistor divider (see Figure 4). First, both channel selection pins associated with that output channel must tied to GND to set the internal reference to 0.6V. Next, the output voltage is set by an external resistive divider according to Equation 1. R2 is selected arbitrarily, but 5k or 10k is usually a good starting point. The designer can configure the output voltage from 1V to 4V from a 5V power supply. Lower input supply voltages reduce the maximum programmable output voltage to 80% of the input voltage level.
V OUT - 0.6V R1 = R2 ---------------------------------0.6V (EQ. 1)
Enable and Disable
If the POR input requirements are met, the ISL65426 remains in shutdown until the voltage at the enable inputs rise above their enable thresholds. Independent enable inputs, EN1 and EN2, allow initialization of either buck converter channel separately, sequenced, or simultaneously. Both pins feature a 10mA pull-up which will initialize both sides once the voltage at their respective pins exceeds the rising enable threshold, as defined in the "Electrical Specifications" table on page 7. Both converters are governed by the presence of a system enable, EN (See Figure 5). When two separate input supplies are used for each channel of power blocks or an external signal needs to govern the power-up sequence, the system enable provides a startup sequencing mechanism. The system enable features an internal 10mA pull-down which is only active when the voltage on the EN pin is below the enable threshold. The current sink pulls the EN pin low. As VCC2 rises the enable level is not set exclusively by the resistor divider from VCC2. With the current sink active, the enable level is defined in Equation 2. R1 is the resistor EN to VCC2 and R2 is the resistor from EN to GND.
Switching Frequency
The controller features an internal oscillator running at a fixed frequency of 1MHz. The oscillator tolerance is +10% over input bias and load range.
Operation Initialization
The ISL65426 initializes based on the state of three enable inputs (EN, EN1, EN2) and power-on reset (POR) monitors on VCC and PVINx inputs. Successful initialization of the controller prompts a one time power block configuration check. Verification of proper phase connections lead to a soft-start interval. The controller begins slowly ramping the output voltages based on the enable input states. Once the 16
FN6340.2 February 21, 2007
ISL65426
0.6V V ENABLE = R1 ------------ + 10A + 0.6V R2
(EQ. 2)
Once the voltage at the EN pin reaches the enable threshold, the 10A current sink turns off. With the part enabled and the current sink off, the disable level is set by the resistor divider. The disable level is defined in Equation 3.
R1 + R2 V DISABLE = 0.6V --------------------R2 (EQ. 3)
common LX connections are checked versus the decoded valid configuration. Each floating power block has a pulldown active only during the configuration check to remove noise related false positive detections. A successful configuration check initiates a soft-start interval 100s after completion. Failing the configuration check, the controller will attempt a configuration check again 100s after completing the first check cycle. The controller repeats the configuration check cycle every 100s until a valid configuration is detected or the controller is powered down. Once successful, the configuration check is not implemented again until VCC falls below the POR falling threshold. Re-enabling the controller after a successful configuration check will immediately initiate a soft-start interval.
The difference between the enable and disable levels provides the user with configurable hysteresis to prevent nuisance tripping. To enable the controller, the system enable must be high, and one or both of the channel enables must be high. The POR circuitry must be satisfied for both VCC and PVINx inputs. Once these conditions are met, the controller immediately initiates a power block configuration check.
ISL65426 EXTERNAL CONDITIONS
Soft-start Interval
Once the controller is enabled and power block configuration is successful, the digital soft-start function clamps the error amplifier reference. The digital soft-start circuitry ramps the output voltage by stepping the reference up gradually over a fixed interval of 4ms. The controlled ramp of the output voltage reduces the in-rush current during startup.
Power Good Signal
+VCC1 VCC
+VCC2 SYSTEM ENABLE COMPARATOR EN POR LOGIC + R2 0.6V 10A R1
Each power good pin (PG1, PG2) is an open-drain logic output which indicates when the converter output voltage is within regulation limits. The power good pins pull low during shutdown and remain low when the controller is enabled. After a successful converter channel soft-start, the power good pin signal associated with that channel releases and the power good pin voltage rises with an external pull-up resistor. The power good signal transitions low immediately upon the removal of individual channel or system enable. The power good circuitry monitors both output voltage FB pins and compares them to the rising and falling limits shown in the "Electrical Specifications" table on page 7. If either channel's feedback voltage exceeds the typical rising limit of 115% of the reference voltage, the power good pin pulls low. The power good pin continues to pull low until the feedback voltage recovers down by a typical of 110% of the reference voltage. If either channel's feedback voltage drops below a typical of 85% of the reference voltage, the power good pin related to the offending channel(s) pulls low. The power good pin continues to pull low until the feedback voltage rises to within 90% of the reference voltage. The power good pin then releases and signals the return of the output voltage within the power good window.
FIGURE 37. SYSTEM ENABLE INPUT
Power Block Configuration Check
After VCC exceeds its POR rising threshold, the controller decodes ISET1 and ISET2 states into one of four valid power block configurations, see Table 1.These pins are not checked again unless VCC falls below the POR falling threshold. The valid configuration is saved for comparison with the LX slave connectivity result determined during the configuration check. Once the POR and enable circuitry is satisfied, the controller initiates a configuration check. The master power block of output Channel 1 (Power Block 2) pulses high for 100ns. The configuration check circuitry detects which power blocks share a common LX connection and compare this to the decoded valid configuration. The master power block of output Channel 2 (Power Block 5) pulses and again the LX pins of the other non-master blocks are monitored. The
Fault Monitoring and Protection
The ISL65426 actively monitors output voltage and current to detect fault conditions. Fault monitors trigger protective measures to prevent damage to the controller and external load device. Individual power good indicators provide options for linking to external system monitors.
17
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ISL65426
Undervoltage Protection
Separate hysteretic comparators monitor the feedback pin (FB) of each converter channel. The feedback voltage is compared to a set undervoltage (UV) threshold based on the output voltage selected. Once one of the comparators trip, indicating a valid UV condition, a 4-bit UV counter increments. If both channel comparators detect an UV condition during the same switching cycle, the 4-bit counter increments twice. Once the 4-bit counter overflows, the UV protection logic shuts down both regulators. The comparator is reset if the feedback voltage rises back up above the UV threshold plus a specified amount of hysteresis outlined in the Electrical Specification Table. If both converter channels experience an UV condition and one rises back within regulation, then the counter continues to progress toward overflow. interval, the OC counter must overflow before the controller shutdowns both outputs again. This hiccup mode continues indefinitely until both outputs soft-start successfully. Note: It is recommended to add a small Schottky diode, part number MBR0520, from LX1 to PGND and from LX5 to PGND to avoid server negative ringing that can disturb the OC counter.
Thermal Monitor
Thermal-overload protection limits total power dissipation in the ISL65426. An internal thermal sensor monitors die temperature continuously. If controller junction temperature exceeds +150C, the thermal monitor commands the POR circuitry to shutdown both channels and latch-off. The POR latch is reset by cycling VCC to the controller.
Overvoltage Response
If the output voltage exceeds the overvoltage (OV) level for the power good signal, the controller will fight this condition by actively trying to regulate the output voltage back down to the reference level. This method of fighting the rise in output voltage is limited by the reverse current capability of the total number of power blocks associated with the output. The approximate reverse current capability of each power block is 0.5A. The power good signal will drop indicating the output voltage is out of specification. This signal will not transition high again until the output voltage has dropped below the falling PGOOD OV threshold.
Component Selection Guide
This design guide is intended to provide a high-level explanation of the steps necessary to create a power converter. It is assumed the reader is familiar with many of the basic skills and techniques referenced below. In addition to this guide, Intersil provides a complete reference design that includes schematic, bill of material, and example board layout.
Output Filter Design
The output inductor and the output capacitor bank together form a low-pass filter responsible for smoothing the pulsating voltage at the phase node. The output filter also must provide the transient energy until the regulator can respond. Because it has a low bandwidth compared to the switching frequency, the output filter limits the system transient response. The output capacitors must supply or sink load current while the current in the output inductors increases or decreases to meet the demand. The output filter is usually the most costly part of the circuit. Output filter design begins with minimizing the cost of these components. OUTPUT CAPACITOR SELECTION The critical load parameters in choosing the output capacitors are the maximum size of the load step (I), the load-current slew rate (di/dt), and the maximum allowable output voltage deviation under transient loading (VMAX). Capacitors are characterized according to their capacitance, ESR (Equivalent Series Resistance), and ESL (Equivalent Series Inductance). At the beginning of the load transient, the output capacitors supply all of the transient current. The output voltage will initially deviate by an amount approximated by the voltage drop across the ESL. As the load current increases, the voltage drop across the ESR increases linearly until the load current reaches its final value. The capacitors selected must have sufficiently low ESL and ESR so that the total output voltage deviation is less than the allowable maximum. Neglecting the contribution of inductor current and regulator response, the output voltage initially deviates by an amount shown in Equation 4.
Overcurrent Protection
A pilot device is integrated into the upper device structure of each master power block. The pilot device samples current through the master power block upper device each cycle. This Channel current feedback is scaled based on the state of the ISET1 and ISET2 pins. The Channel current information is compared to an overcurrent (OC) limit based on the power block configuration. Each 1A power block tied to the master power block increases the OC limit by 2A. For example, if both masters have two slaves associated with each of them then the OC limit for each output is 6A for a 3A configuration. If the sampled current exceeds the OC threshold, a 4-bit OC up/down counter increments by one LSB. If the sampled current falls below the OC threshold before the counter overflows, the counter is reset. If both regulators experience an OC event during the same cycle, the counter increments twice. Once the OC counter reaches 1111, both channels are shutdown. If both channels fall below the over-current limit during the same cycle, the OC counter is reset. Once in shutdown, the controller enters a delay interval, equivalent to the SS interval, allowing the die to cool. The OC counter is reset entering the delay interval. The protection logic initiates a normal SS internal once the delay interval ends. If the outputs both successfully soft-start, the power good signal goes high and normal operation continues. If OC conditions continue to exist during the SS 18
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ISL65426
di V ESL x ---- + [ ESR x I ] dt ( 1.25 ) C L ------------------------ V MAX - ( I ESR ) V IN - V O ( I ) 2 (EQ. 9)
(EQ. 4)
The filter capacitor must have sufficiently low ESL and ESR so that V < VMAX. Most capacitor solutions rely on a mixture of high frequency capacitors with relatively low capacitance in combination with bulk capacitors having high capacitance but limited high-frequency performance. Minimizing the ESL of the high-frequency capacitors allows them to support the output voltage as the current increases. Minimizing the ESR of the bulk capacitors allows them to supply the increased current with less output voltage deviation. The ESR of the bulk capacitors also creates the majority of the output voltage ripple. As the bulk capacitors sink and source the inductor AC ripple current, a voltage develops across the bulk capacitor VPPMAX. See Equation 5.
V PP ( V IN - V OUT )V OUT = ESR x ---------------------------------------------------L x f s x V IN (EQ. 5)
The other concern when selecting an output inductor is the internally set current mode slope compensation. Designs should not allow inductor ripple currents below 0.125 times the maximum output current to prevent regulation issues. A good rule of thumb for selection of the output inductance value is 1/3 of the maximum load current for inductor ripple.
(V - V )xV IN OUT OUT L -------------------------------------------------------------I OUT MAX V x f x ----------------------------IN s 3
(EQ. 10)
The rule of thumb value, see Equation 10, with fall between the minimum inductance value calculated in Equation 7 and the maximum values determined from Equations 8 and 9.
Input Capacitor Selection
Input capacitors are responsible for sourcing the AC component of the input current flowing into the switching power devices. Their RMS current capacity must be sufficient to handle the AC component of the current drawn by the switching power devices which is related to duty cycle. The maximum RMS current required by the regulator is closely approximated by Equation 11.
I RMS = MAX 2 V OUT 2 1 V IN - V OUT V OUT ----------------- x I ------------------------------------- x ----------------- OUT MAX + 12 x V IN L x fs V IN
MAX
The recommended load capacitance recommended is based on Equation 6.
C OUT = 0.5 x I OUT x 100F (EQ. 6)
MAX
(EQ. 11)
OUTPUT INDUCTOR SELECTION Once the output capacitors are selected, the maximum allowable ripple voltage, VPPMAX, determines the lower limit on the inductance. See Equation 7.
( V IN - V OUT )V OUT L ESR x ---------------------------------------------------f s x V IN x V PP
MAX
(EQ. 7)
The important parameters to consider when selecting an input capacitor are the voltage rating and the RMS current rating. For reliable operation, select capacitors with voltage ratings above the maximum input voltage. Their voltage rating should be at least 1.25 times greater than the maximum input voltage, while a voltage rating of 1.5 times is a conservative guideline. The capacitor RMS current rating should be higher than the largest RMS current required by the circuit.
Since the output capacitors are supplying a decreasing portion of the load current while the regulator recovers from the transient, the capacitor voltage becomes slightly depleted. The output inductors must be capable of assuming the entire load current before the output voltage decreases more than VMAX. This places an upper limit on inductance. Equation 8 gives the upper limit on output inductance for the cases when the trailing edge of the current transient causes the greater output voltage deviation than the leading edge. Equation 9 addresses the leading edge. Normally, the trailing edge dictates the inductance selection because duty cycles are usually less than 50%. Nevertheless, both inequalities should be evaluated, and inductance should be governed based on the lower of the two results. In each equation, L is the output inductance and C is the total output capacitance.
2 C VO L ------------------------ V MAX - ( I ESR ) ( I ) 2 (EQ. 8)
Layout Considerations
Careful printed circuit board (PCB) layout is critical in highfrequency switching converter design. Current transitions from one device to another at this frequency induce voltage spikes across the interconnecting impedances and parasitic elements. These spikes degrade efficiency, lead to device overvoltage stress, radiate noise into sensitive nodes, and increase thermal stress on critical components. Careful component placement and PCB layout minimizes the voltage spikes in the converter. The following multi-layer printed circuitry board layout strategies minimize the impact of board parasitics on converter performance and optimize the heat-dissipating capabilities of the printed circuit board. This section highlights some important practices which should not be overlooked during the layout process. Figure 6 provides a top level view of the critical components, layer utilization, and signal routing for reference.
FN6340.2 February 21, 2007
19
ISL65426
Component Placement
Determine the total implementation area and orient the critical switching components first. These include the controller, input and output capacitors, and the output inductors. Symmetry is very important in determining how available space is filled and depends on the power block configuration selected. The controller must be placed equidistant from each output stage with the LX, or phase, connection distance minimized. An output stage consists of the area reserved for the output inductor, and input capacitors, and output capacitors for a single channel. Place the inductor such that one pad is a minimal distance from the associated phase connection. Orient the inductor such that the load device is a short distance from the other pad. Placement of the input capacitors a minimal distance from the PVIN pins prevents long distances from adding too much trace inductance and a reduction in capacitor performance. Locate the output capacitors between the inductor and the load device, while keeping them in close proximity. Care should be taken not to add inductance through long trace lengths that could cancel the usefulness of the low inductance components. Keeping the components in tight proximity will help reduce parasitic impedances once the components are routed together. Bypass capacitors, CBP, supply critical filtering and must be placed close to their respective pins. Stray trace parasitics will reduce their effectiveness, so keep the distance between the VCC bias supply pad and capacitor pad to a minimum. usually an internal layer underneath the component side of the board, for a ground plane and make all critical component ground connections with vias to this layer. One additional solid layer is dedicated as a power plane and broken into smaller islands of common voltage. The power plane should support the input power and output power nodes. Use copper filled polygons on the top and bottom circuit layers for the phase nodes. Use the remaining printed circuit board layers for small signal wiring and additional power or ground islands as required.
Signal Routing
If the output stage component placement guidelines are followed, stray inductance in the switch current path is minimized along with good routing techniques. Great attention should be paid to routing the PHASE plane since high current pulses are driven through them. Stray inductance in this high-current path induce large noise voltages that couple into sensitive circuitry. By keeping the PHASE plane small, the magnitude of the potential spikes is minimized. It is important to size traces from the LX pins to the PHASE plane as large and short as possible to reduce their overall impedance and inductance. Sensitive signals should be routed on different layers or some distance away from the PHASE plane on the same layer. Crosstalk due to switching noise is reduced into these lines by isolating the routing path away from the PHASE plane. Layout the PHASE planes on one layer, usually the top or bottom layer, and route the voltage feedback traces on another layer remaining.
Plane Allocation
PCB designers typically have a set number of planes available for a converter design. Dedicate one solid layer,
VIN VCC CBP PVIN
VIN
KEY THICK TRACE ON CIRCUIT PLANE LAYER ISLAND ON CIRCUIT PLANE LAYER
CIN
ISLAND ON POWER PLANE LAYER VIA CONNECTION TO GROUND PLANE
ISL65426
LX
PHASE
LOUT
VOUT
COUT GND
CHFOUT
LOAD
FB
PGND
FIGURE 38. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS
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ISL65426
Thermal Management
For maximum thermal performance in high current, high switching frequency applications, connecting the thermal PGND pad of the ISL65426 to the ground plane with multiple vias is recommended. This heat spreading allows the IC to achieve its full thermal potential. If possible, place the controller in a direct path of any available airflow to improve thermal performance.
21
FN6340.2 February 21, 2007
ISL65426 L50.5x10
50 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 0, 7/06
5.00
A B
4
0.10 M C A B 0.05 M C 0.25 43 42 0.50 50 1 PIN 1 INDEX AREA (C 0.40)
A
PIN 1 INDEX AREA
0.50x16=8.00 REF
10.00
8.10
26
17 25 3.30 18 0.400.10 SEE DETAIL "X" 0.10 C C SEATING PLANE 0.08 C 5
A
0.15 (4X)
VIEW "A-A"
0.400.10
0.50x7=3.50 REF 4.20
TOP VIEW
BOTTOM VIEW
SIDE VIEW
MAX. 1.00 9.80 C 0.2 REF
8.10
(46 x 0.50)
0.00 MIN. 0.05 MAX.
DETAIL "X"
(50 x 0.25)
NOTES: 1. CONTROLLING DIMENSIONS ARE IN MM.
(50 x 0.60) 3.30 4.80
2. UNLESS OTHERWISE SPECIFIED TOLERANCE : DECIMAL 0.05 ANGULAR 2x 3. DIMENSIONING AND TOLERANCE PER ASME Y 14.5M-1994. 4. DIMENSION LEAD WIDTH APPLIES TO THE PLATED TERMINAL AND IS MEASURED BETWEEN 0.23MM AND 0.28MM FROM THE TERMINAL TIP. 5. TIEBAR SHOWN (if present) IS A NON-FUNCTIONAL FEATURE
RECOMMENDED LAND PATTERN
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 22
FN6340.2 February 21, 2007
0.50
9.20

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